1. Field of the Invention
The present invention relates to a sense amplifier of a semiconductor memory device, and more particularly, to a power down circuit of a sense amplifier that prevents undesirable power consumption.
2. Background of the Related Art
As shown in FIG. 1, a related art sense amplifier circuit in a semiconductor memory device includes an automatic power down unit 1 for outputting a sense amplifier enable signal (SEN) upon receiving an address transition detection signal (ATD) outputted from an address transition detector (not illustrated), a first sense amplifier 2 for performing a sensing operation upon receiving the sense amplifier enable signal (SEN) outputted from the automatic power down unit 1, and a second sense amplifier 3 for sensing more completely the data sensed in the first sense amplifier 2.
The first sense amplifier 2 includes PMOS transistors 20, 21 that receive a voltage source (Vcc) and having commonly coupled gates to form a current mirror. A PMOS transistor 22 has its source coupled to a node where the gate and the drain of the PMOS transistor 20 are commonly coupled, its drain coupled to the drain of the PMOS transistor 21 and its gate receiving an equalization (EQN) signal. An NMOS transistor 23 has its drain coupled to the source of the PMOS transistor 22 and its gate receives a data bar signal (DB). An NMOS transistor 24 has its drain coupled to the drain of the PMOS transistor 22, the gate receives a data (D) and the source coupled to the source of the NMOS transistor 23. Further, PMOS transistors 25, 26, 27 and NMOS transistors 28, 29 are coupled using the same structure as the PMOS transistors 20, 21, 22 and the NMOS transistors 23, 24. An NMOS transistor 30 has its drain coupled to the commonly coupled sources of the NMOS transistors 23, 24, 28, 29, its source coupled to ground and its gate receiving the sense amplifier enable signal (SEN).
The second sense amplifier 3 includes PMOS transistors 31, 32, 33 and NMOS transistors 34, 35 coupled using the same structure as the PMOS transistors 20, 21, 22 and the NMOS transistors 23, 24. The second sense amplifier also includes an NMOS transistor 36 having its drain coupled to the commonly coupled sources of the NMOS transistors 34, 35 its gate receives the sense amplifier enable signal (SEN) and the source is grounded.
The operation of the related art sense amplifier of the semiconductor memory device will now be described with reference to FIGS. 1 and 2.
First, the address transition detection signal (ATD) shown in FIG. 2A outputted from the address transition detector (not illustrated) in accordance with the transition of an address signal (not illustrated) is inputted to the automatic power down unit 1. Then, the automatic power down unit 1 generates an auto power down signal (APD) as shown in FIG. 2B and outputs the sense amplifier enable signal (SEN) extended by a predetermined width as shown in FIG. 2C.
Then, as shown in FIG. 2D, when the equalization signal (EQN) is enabled to be low, the PMOS transistors 22, 27, 33 are turned on, whereby an electric potential of each pair of nodes (N1 and N2, N3 and N4, N5 and N6) comes to have an identical value. Then, when the equalization signal (EQN) is disabled to be high, the PMOS transistors 22, 27, 33 are turned off to complete the equalization operation.
As described above, at the point when the equalization operation is completed, that is, when the equalization signal (EQN) is made high and the sense amplifier enable signal (SEN) is high, the sense amplifiers 2, 3 start sensing.
First, sense amplifier enable transistors 30, 36 (i.e., the NMOS transistors 30, 36) are turned on in accordance with the high sense amplifier enable signal (SEN) and then the PMOS transistors 22, 27, 33 are turned off in accordance with the high equalization signal (EQN). Next, when the data signal (D) and the data bar signal (DB) are as shown in FIG. 2E, the NMOS transistor 24 is turned on more fully than the NMOS transistor 23. As a result, more current flows through the NMOS transistor 24 than the NMOS transistor 23 and the electrical potential of the node (N2) is lowered relative to the node (N1).
In the same way, the data (D) signal is inputted to the gate of the NMOS transistor 28, and the data bar (DB) signal is inputted to the gate of the NMOS transistor 29. As a result, since more current flows through the NMOS transistor 28 than through the NMOS transistor 29, the electrical potential of the node (N3) is lowered relative to that of the node (N4).
The gate of the NMOS transistor 35 of the second sense amplifier 3 receives the low level of the node (N2) and the gate of the NMOS transistor 34 is applied with the high level of the node (N4). Therefore, the electrical potential of the node (N5) is lowered relative to that of the node (N6).
Accordingly, as shown in FIG. 2F, the data signal and the data bar signal that are difficult to be respectively recognized completely as high and low can be outputted as signals recognizable as high (SAOUT) and low (SAOUTB).
However, in the related art sense amplifier of the semiconductor memory device, the sense amplifier continues to operate while a sense amplifier enable pulse signal (SEN) outputted from the automatic power down unit 1 is high level, and an unnecessary sensing current continues flowing even when the sensing is quickly completed, which results in increasing power consumption.